The accurate measurement of the frequency and phase of received signals is important in systems such as radar range and range rate measurement, navigation, and collision avoidance systems. It is also useful in communication systems for extracting bit timing information to permit synchronous detection of digital data streams.
Phase locked oscillators (PLO) provide the preferred techniques for producing accurate measurement of phase and frequency. Basically, a phase locked oscillator compares the phase of an input signal to the phase of a voltage controlled oscillator (VCO). The resultant phase difference modifies the control voltage of the VCO to change its frequency in a direction that reduces the phase difference.
The accuracy of a PLO can be increased by using digital techniques. The accuracy of a digital system increases with the number of bits used. Frequency limitations are imposed, however, by the speed of the digital devices employed in the system.
An important component of the digital PLO systems is the generation of a frequency which is controlled by a digital number. The digital number is usually a function of the phase difference between the VCO output signal and the received signal. Comparison of the various available techniques is more clear when applied to a specific example. In the discussion below, a doppler frequency extractor will be used as the example. Doppler frequency shift is important in determining range rate and is the change of the input frequency from a transmitted or reference signal or from its previous value.
One PLO technique is Programmable-Divide-by-N in which the frequency of a reference oscillator is divided and compared to the divided phase difference between the received signal and the VCO output signal. Varying the division ratios varies the frequency of the VCO.
If the VCO frequency (f.sub.s) is divided by N and the reference frequency (f.sub.R) is divided by R , then the VCO output frequency will be EQU f.sub.s = (N/R)f.sub.R.
comparing the phase of the VCO output signal to the phase of the received signal produces a phase difference which is converted to a digital number by an analog-to-digital converter. The resulting digital number is N and controls the frequency of the VCO to track the received signal. The value of N will be proportional to the received frequency.
The required sampling rate (f.sub.R /R) can be found for a given degree of accuracy in the measurement of doppler shift. Assuming a 19MHz transponder output frequency and letting f.sub.d /110.5 represent the doppler shift on the 19MHz interface, EQU 19 .times. 10.sup.6 + f.sub.d /110.5 = (N/R)f.sub.R.
when f.sub.d is zero, N will have a nominal value. Designating this value N.sub.o, EQU 19 .times. 10.sup.6 + f.sub.d /110.5 = (N.sub.o + n)f.sub.R /R
where n is the change in N.sub.o required to track f.sub.d. For an accuracy of 0.01Hz accuracy, a unit change in n, which is an integer, must result in a 0.01Hz change. Therefore, since N.sub.o (f.sub.R /R ) = 19 .times. 10.sup.6, EQU f.sub.d /110.5 = n(f.sub.R /R)
and for n = 1 and fd = 0.01Hz, EQU f.sub.R /R = 10.sup.-.sup.4 Hz.
The low pass filter which couples the comparator output signal to the VCO must limit the passed frequencies to approximately one-tenth the sampling frequency to suppress incidental frequency modulation at the sampling frequency. In the above example, the bandwidth of the filter would be approximately 10.sup.-.sup.5 Hz which is prohibitively narrow for implementation and for requirements of initial acquisition and tracking of doppler rates. Furthermore, frequency variations in the VCO would prevent the system from remaining locked to f.sub.R /R.
Averaging the value of n over several samples will not improve the resolution because n will not change faster than R/f.sub. R, which is 10.sup.4 seconds (2 hours, 46 minutes, 40 seconds) in the above example.
This technique requires at least a 30-bit divider, the minimum attained by translating the 19MHz interface to only 100KHz.
For the above reasons, a programmable divider PLO has serious limitations of accuracy.
A second technique, called Iterative Synthesizing, combines frequencies obtained by division of reference frequencies. The combinations are controlled by a digital number so that the resulting output frequency is proportional to the digital number.
Practical iterative synthesizers have high resolution, wide tuning range, and high spectral purity. The system, however, requires a large amount of hardware. A system having the resolution of 0.01Hz discussed in the above example would require 12 mixers, five different input frequencies each with a fixed frequency synthesizer, 48 frequency selection switches or gates, and 24 low-pass filters.
A third PLO technique uses an Incremental Phase Modulator to generate a controlled frequency offset from a given reference frequency. The offset is controlled by a digital number. An example of the implementation of this technique would be a tapped delay line, the output signal from each tap coupled to a gate which is enabled by one of the bits in the controlling digital number. The output signals from all the gates would be combined in a mixer to produce the output frequency. This implementation is called a Serradyne. The frequency at which this technique operates is determined by the number of taps, phase quantization, and the stability of the tapped delay line. The complexity of the implementation makes this technique unattractive for high resolution systems.
A fourth PLO technique, which is sometimes referred to as direct synthesization, employs an arithmetic synthesizer to construct a sine wave signal by accumulation of the digital number. A VCO is not used in this technique; the output signal is synthesized by the accumulator. An example of a direct arithmetic synthesizer can be found in U.S. Pat. No. 3,689,914 (Butler), assigned to the same assignee as this application. An example of the use of an arithmetic synthesizer used in a locked loop can be found in application Ser. No. 609,004, assigned to the same assignee as this application. In this technique, the digital number is added into an accumulator periodically in response to a clock signal. The accumulator contents increase linearly until the capacity of the accumulator is exceeded. At this point, the accumulator overflows and begins to increase linearly again. The successive numbers in the accumulator, if plotted graphically, represent a sawtooth waveform. Successive carries from the accumulator can be used to complement the accumulator's output signal which results in a step-wise triangular wave shape. This waveform (or the sawtooth) can be filtered to extract the fundamental frequency. By filtering out the step levels, a relatively pure sine wave can be generated.
If the accumulator capacity is designated N.sub.c, the synthesized frequency is EQU f.sub.s = (N.sub.R /N.sub.c)f.sub.o,
where N.sub.R = register (frequency) number (controlling digital number), and
f.sub.o = frequency of the clock signal.
Multiplying the synthesized output signal by K before applying it to the phase comparator reduces the synthesizer frequency and the frequency requirements of the clock signal for a given VCO frequency. The reduction of the clock frequency is necessary at high frequencies because of the limitations imposed by the adder speed. The value of K is referred to as the frequency multiplying ratio. The synthesized frequency is EQU f.sub.s = K(N.sub.R /N.sub.c)f.sub.o.
Since N.sub.R, N.sub.c, and K are integers, only discrete frequencies can be generated for a fixed clock frequency. The accuracy can be selected by proper selection of the multiplying ratio, the accumulator capacity, and the clock frequency. With N.sub.c, f.sub.o, and K fixed, the smallest change in output frequency is the result of a unit change in the digital number, N.sub.R. Therefore, EQU .DELTA.f.sub.s = Kf.sub.o /N.sub.c.
For a transponder interface frequency of 76MHz, a clock frequency of 5MHz, and a synthesizer output frequency of 1MHz, the value of the multiplier ratio is 76. For a 0.01Hz frequency change in the S-band, or a 3.62 .times. 10.sup.-.sup.4 Hz change at 76MHz, the accumulator capacity is calculated by EQU 3.62 .times. 10.sup.-.sup.4 = 76 .times. 5 .times. 10.sup.6 /N.sub.c.
Therefore, EQU N.sub.c = 1.05 .times. 10.sup.12
and the number of bits required is given by EQU B.sub.c = log.sub.2 N.sub.c = 39.933
which indicates 40 bits are required.
The primary disadvantage of an arithmetic synthesizer is the inability to operate at high speed without using special logic circuits. Other problems are caused by spurious signals introduced by the accumulator overflows and quantization noise added by the finite resolution of the digital-to-analog converter that converts the digital number from the accumulator to the analog output signal.
The invention disclosed herein is a system implementation for extracting very accurate phase and frequency information from a received signal using a digital direct arithmetic synthesizer locked to the received signal through a wideband digital feedback loop.